The general delay locked loop, as shown in FIG. 1A includes a clock generator 101 generating a system clock 105, a delay array 102 receiving system clock 105 for providing a delayed clock 106, a phase detector 103 for detecting a phase difference 108 between system clock 105 and delayed clock 106, and a counter 104 generating a control signal 107 in response to phase difference 108 for enabling delay array 102 to determine how many delay elements should be used.
FIG. 1B shows the delay locking situation according to the prior delay locked loop. If the rising edge of delayed clock 106 falls within the safe delay locking range as shown, phase detector 103 will compare rising edges of system clock 105 and delayed clock 106 such that phase difference has a positive value when the rising edge of delayed clock 106 leads that of system clock 105, and has a negative value when the former is lagged beyond the latter. Counter 104 will adjust a delay time according to the value of phase difference 108 to provide control signal 107 for controlling delay device 102 to output appropriate delayed clock 106.
On the contrary, if the rising edge of delayed clock 106 does not fall within the shown safe delay locking range, phase difference 108 obtained through phase detector 103 cannot reflect the real situation so as to result in a system error. In other words, the rising edge of delayed clock 106 must be located within the shown safe delay locking range in order that the system can normally function. In addition, the initial output value of counter 104 must be properly selected to neatly cope with process deviation as well as temperature and voltage shifts for appropriate system operations in different frequencies. All these requirements cannot be duly met by the prior delay locked loop.
It is therefore tried by the applicant to deal with the above situation encountered by the prior art.